一天一个设计实例-静态随机存储器 SRAM 的 Verilog HDL/VHDL语言描述 / 四六文摘

静态随机存储器 SRAM 的 Verilog HDL语言描述

代码3‑1 SRAM 的 Verilog HDL语言描述

1.//****************************************************************************//

2.//# @Author: 碎碎思

3.//# @Date: 2019-04-01 20:39:25

4.//# @Last Modified by: zlk

5.//# @WeChat Official Account: OpenFPGA

6.//# @Last Modified time: 2019-04-01 22:20:36

7.//# Description:

8.//# @Modification History: 2019-04-01 22:20:36

9.//# Date By Version Change Description:

10.//# ========================================================================= #

11.//# 2019-04-01 22:20:36

12.//# ========================================================================= #

13.//# | | #

14.//# | OpenFPGA | #

15.//****************************************************************************//

16.module savemod_demo

17.(

18. CLOCK,

19. RESET,

20. LED,

21.

22.

23. SRAM_A,

24. SRAM_DB,

25. SRAM_WE_N,

26. SRAM_OE_N,

27. SRAM_UB_N,

28. SRAM_LB_N,

29. SRAM_CE_N

30.

31.

32.);

33.

34.

35.

36. input CLOCK,RESET;

37.

38. output reg [3:0]LED;

39.

40.

41.

42. output reg[17:0]SRAM_A; //2^18 == 256K

43. inout [15:0]SRAM_DB;

44. output SRAM_WE_N; //sram write enable

45. output SRAM_OE_N; //sram output enable

46. output SRAM_UB_N; //sram Upper-byte control(IO15-IO8)

47. output SRAM_LB_N; //sram Lower-byte control(IO7-IO0)

48. output SRAM_CE_N; //sram Chip enable

49.

50.////////////////////////////////////////////

51.reg[25:0] delay; //延时计数器，不断计数，周期约为1.34s，用于产生定时信号。

52.

53.always @ (posedge CLOCK or negedge RESET)

54. if(!RESET) delay <= 26'd0;

55. else delay <= delay+1;

56.

57.////////////////////////////////////////////

58.wire sram_wr_req; // SRAM写请求信号，高电平有效，用于状态机控制。

59.wire sram_rd_req; // SRAM读请求信号，高电平有效，用于状态机控制。

60.

61.

62.reg[15:0] wr_data; // SRAM写入数据寄存器。

63.reg[15:0] rd_data; // SRAM读出数据寄存器。

64.

65.

66.assign sram_wr_req = (delay == 26'd9999); //产生写请求信号

67.assign sram_rd_req = (delay == 26'd19999); //产生读请求信号

68.

69.always @ (posedge CLOCK or negedge RESET) //写入数据每1.34s自增1。

70. if(!RESET) wr_data <= 16'd0;

71. else if(delay == 26'd29999) wr_data <= wr_data+1'b1;

72.

73.always @ (posedge CLOCK or negedge RESET) //写入地址每1.34s自增1。

74. if(!RESET) SRAM_A <= 18'd0;

75. else if(delay == 26'd29999) SRAM_A <= SRAM_A+1'b1;

76.

77.always @ (posedge CLOCK or negedge RESET) //每1.34s比较一次同一地址写入和读出的数据。

78. if(!RESET) LED[0] <= 1'b0;

79. else if(delay == 26'd20099) begin

80. if(wr_data == rd_data) LED[0] <= 1'b1; //写入和读出数据一致，LED点亮

81. else LED[0] <= 1'b0; //写入和读出数据不同，LED熄灭

82. end

83.

84.

85.////////////////////////////////////////////

86.//状态机控制SRAM的读或写操作。

87.parameter IDLE = 4'd0,

88. WRT0 = 4'd1,

89. WRT1 = 4'd2,

90. REA0 = 4'd3,

91. REA1 = 4'd4;

92.

93.reg[3:0] cstate,nstate;

94.

95.////////////////////////////////////////////

96.`define DELAY_80NS (cnt==3'd7) //用于产生SRAM读写时序所需要的延时。

97.

98.reg[2:0] cnt; //延时计数器

99.

100.always @ (posedge CLOCK or negedge RESET)

101. if(!RESET) cnt <= 3'd0;

102. else if(cstate == IDLE) cnt <= 3'd0;

103. else cnt <= cnt+1'b1;

104.

105.////////////////////////////////////////////

106.always @ (posedge CLOCK or negedge RESET) //时序逻辑控制状态变迁。

107. if(!RESET) cstate <= IDLE;

108. else cstate <= nstate;

109.

110.always @ (cstate or sram_wr_req or sram_rd_req or cnt) begin //组合逻辑控制不同状态的转换。

111. case (cstate)

112. IDLE: if(sram_wr_req) nstate <= WRT0; //进入写状态。

113. else if(sram_rd_req) nstate <= REA0; //进入读状态。

114. else nstate <= IDLE;

115. WRT0: if(`DELAY_80NS) nstate <= WRT1;

116. else nstate <= WRT0;

117. WRT1: nstate <= IDLE;

118. REA0: if(`DELAY_80NS) nstate <= REA1;

119. else nstate <= REA0;

120. REA1: nstate <= IDLE;

121. default: nstate <= IDLE;

122. endcase

123.end

124.

125.////////////////////////////////////////////

126.//SRAM读写数据的控制。

127.reg sdlink; // SRAM数据总线方向控制信号，改值取1为输出，取0为输入。

128.

129.always @ (posedge CLOCK or negedge RESET) //在状态REA1时执行SRAM读数据操作。

130. if(!RESET) rd_data <= 16'd0;

131. else if(cstate == REA1) rd_data <= SRAM_DB;

132.

133.always @ (posedge CLOCK or negedge RESET) //控制不同状态下SRAM数据总线的方向。SRAM只有在执行写操作时为输出，其他时候均为输入。

134. if(!RESET) sdlink <=1'b0;

135. else begin

136. case (cstate)

137. IDLE: if(sram_wr_req) sdlink <= 1'b1;

138. else if(sram_rd_req) sdlink <= 1'b0;

139. else sdlink <= 1'b0;

140. WRT0: sdlink <= 1'b1;

141. default: sdlink <= 1'b0;

142. endcase

143. end

144.

145.assign SRAM_DB = sdlink ? wr_data : 16'hzzzz;

146.//assign SRAM_WE_N = ~sdlink;

147.

148.

149.

150.assign SRAM_UB_N = 1'b0;

151.assign SRAM_LB_N = 1'b0;

152.assign SRAM_CE_N = 1'b0;

153.assign SRAM_WE_N = (~sdlink ? 1'b1 : 1'b0);

154.assign SRAM_OE_N = (~sdlink ? 1'b0 : 1'b1);

155./*SRAM读写结束*/

156.

157.endmodule

静态随机存储器 SRAM 的 VHDL语言描述

代码3‑2 SRAM 的 VHDL语言描述

1.library IEEE;

2.use IEEE.std_logic_1164.all;

3.use IEEE.std_logic_arith.all;

4.use IEEE.std_logic_unsigned.all;

6.entity sram_test is

7. port(

8. clk: in STD_LOGIC;

9. rst_n: in STD_LOGIC;

10. led: out STD_LOGIC;

11. sram_addr: buffer STD_LOGIC_VECTOR (14 downto 0);

12. sram_wr_n: out STD_LOGIC;

13. sram_data: inout STD_LOGIC_VECTOR (7 downto 0)

14. );

15.end entity sram_test;

16.

17.architecture sram_randw of sram_test is

18. signal delay: STD_LOGIC_VECTOR (25 downto 0);

19. signal wr_data: STD_LOGIC_VECTOR (7 downto 0);

20. signal rd_data: STD_LOGIC_VECTOR (7 downto 0);

21. signal sram_wr_req: STD_LOGIC;

22. signal sram_rd_req: STD_LOGIC;

23. signal cnt: STD_LOGIC_VECTOR (2 downto 0);

24. type state is (IDLE,WRT0,WRT1,REA0,REA1);

25. signal cstate: state;

26. signal nstate: state;

27. signal sdlink: STD_LOGIC;

28.begin

29.----------------------

30. process(clk,rst_n)

31. begin

32. if (rst_n = '0') then

33. delay <= "00" & x"000000";

34. elsif (clk'event AND clk = '1') then

35. delay <= delay+1;

36. end if;

37. end process;

38. sram_wr_req <= '1' when (delay = 10#9999#) else

39. '0';

40. sram_rd_req <= '1' when (delay = 10#19999#) else

41. '0';

42.----------------------

43. process(clk,rst_n)

44. begin

45. if (rst_n = '0') then

46. wr_data <= x"00";

47. elsif (clk'event AND clk = '1') then

48. if(delay = 10#29999#) then

49. wr_data <= wr_data+'1';

50. end if;

51. end if;

52. end process;

53.

54. process(clk,rst_n)

55. begin

56. if (rst_n = '0') then

57. sram_addr <= "000" & x"000";

58. elsif (clk'event AND clk = '1') then

59. if(delay = 10#29999#) then

60. sram_addr <= sram_addr+'1';

61. end if;

62. end if;

63. end process;

64.

65. process(clk,rst_n)

66. begin

67. if (rst_n = '0') then

68. led <= '0';

69. elsif (clk'event AND clk = '1') then

70. if(delay = 10#20099#) then

71. if(wr_data = rd_data) then

72. led <= '1';

73. else

74. led <= '0';

75. end if;

76. end if;

77. end if;

78. end process;

79.----------------------

80. process(clk,rst_n)

81. begin

82. if (rst_n = '0') then

83. cnt <= "000";

84. elsif (clk'event AND clk = '1') then

85. if(cstate = IDLE) then

86. cnt <= "000";

87. else

88. cnt <= cnt+'1';

89. end if;

90. end if;

91. end process;

92.----------------------

93. process(clk,rst_n)

94. begin

95. if (rst_n = '0') then

96. cstate <= IDLE;

97. elsif (clk'event AND clk = '1') then

98. cstate <= nstate;

99. end if;

100. end process;

101.

102. process(cstate,sram_wr_req,sram_rd_req,cnt)

103. begin

104. case cstate is

105. when IDLE =>

106. if (sram_wr_req = '1') then

107. nstate <= WRT0;

108. elsif (sram_rd_req = '1') then

109. nstate <= REA0;

110. else

111. nstate <= IDLE;

112. end if;

113. when WRT0 =>

114. if (cnt = "111") then

115. nstate <= WRT1;

116. else

117. nstate <= WRT0;

118. end if;

119. when WRT1 =>

120. nstate <= IDLE;

121. when REA0 =>

122. if (cnt = "111") then

123. nstate <= REA1;

124. else

125. nstate <= REA0;

126. end if;

127. when REA1 =>

128. nstate <= IDLE;

129. when others =>

130. nstate <= IDLE;

131. end case;

132. end process;

133.----------------------

134. process(clk,rst_n)

135. begin

136. if (rst_n = '0') then

137. rd_data <= x"00";

138. elsif (clk'event AND clk = '1') then

139. if (cstate = REA1) then

140. rd_data <= sram_data;

141. end if;

142. end if;

143. end process;

144.

145. process(clk,rst_n)

146. begin

147. if (rst_n = '0') then

148. sdlink <= '0';

149. elsif (clk'event AND clk = '1') then

150. case cstate is

151. when IDLE =>

152. if (sram_wr_req = '1') then

153. sdlink <= '1';

154. elsif (sram_rd_req = '1') then

155. sdlink <= '0';

156. else

157. sdlink <= '0';

158. end if;

159. when WRT0 =>

160. sdlink <= '1';

161. when others =>

162. sdlink <= '0';

163. end case;

164. end if;

165. end process;

166. sram_data <= wr_data when (sdlink = '1') else

167. "ZZZZZZZZ";

168. sram_wr_n <= NOT sdlink;

169.end architecture sram_randw;

一天一个设计实例-静态随机存储器 SRAM 的 Verilog HDL/VHDL语言描述

静态随机存储器 SRAM 的 VHDL语言描述

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